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Power-conscious test synthesis and scheduling

Nicolici, Nicola and Al-Hashimi, Bashir M (2002) Power-conscious test synthesis and scheduling IEEE Design & Test of Computers, 20, (4), pp. 48-55.

Record type: Article

Abstract

BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and scheduling affect power dissipation and present new power-conscious algorithms.

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More information

Published date: July 2002
Additional Information: A preliminary version of this paper has won "Besaung Best Paper Award", IEEE International Test Conference 2000
Keywords: Low power VLSI test
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 258330
URI: http://eprints.soton.ac.uk/id/eprint/258330
ISSN: 0740-7475
PURE UUID: bd4f3eb7-d38e-4c3d-bea8-b82ad00cee50

Catalogue record

Date deposited: 10 Oct 2003
Last modified: 18 Jul 2017 09:33

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Contributors

Author: Nicola Nicolici

University divisions

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