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Dual multiple-polynomial LFSR for low-pwoer mixed-mode BIST

Record type: Article

Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation during BIST. A new mixed-mode test pattern generator is proposed with reduced power when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LSFR reseeding. Extensive experiments were preformed using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved.

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Citation

Rosinger, Paul, Al-Hashimi, Bashir M and Nicolici, Nicola (2003) Dual multiple-polynomial LFSR for low-pwoer mixed-mode BIST IEE Proceedings: Computers and Digital Techniques, 150, (4), pp. 209-218.

More information

Published date: July 2003
Keywords: low power VLSI test, BIST
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 258332
URI: http://eprints.soton.ac.uk/id/eprint/258332
ISSN: 1350-2387
PURE UUID: 964eb7d4-27ef-4705-a747-49df9577e05b

Catalogue record

Date deposited: 10 Oct 2003
Last modified: 18 Jul 2017 09:33

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Contributors

Author: Paul Rosinger
Author: Nicola Nicolici

University divisions


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