Addressing Useless Test Data in Core-Based System-on-a-Chip Test
Addressing Useless Test Data in Core-Based System-on-a-Chip Test
This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and it leads to the trade-off between the test bus width and the volume of test data in multiple scan chains-based cores. Ultimately this trade-off influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed, which by dividing the wrapper scan chains into two or more partitions, and by exploiting automated test equipment memory management features reduces the useless memory. Extensive experimental results using ISCAS89 and ITC02 benchmark circuits are provided to analyze the implications of the number of wrapper scan chains in the partition, and the number of partitions on the proposed methodology.
Core-based test, core wrapper design, embedded core test, system-on-a-chip (SOC), useless test data, volume of test data
1568-1590
Gonciari, PT
f6d44d5f-c2e0-479a-b609-b0245faa01f9
Al-Hashimi, B
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, N
7cb1f38a-3d14-43fb-9b79-aa0f4d106372
November 2003
Gonciari, PT
f6d44d5f-c2e0-479a-b609-b0245faa01f9
Al-Hashimi, B
0b29c671-a6d2-459c-af68-c4614dce3b5d
Nicolici, N
7cb1f38a-3d14-43fb-9b79-aa0f4d106372
Gonciari, PT, Al-Hashimi, B and Nicolici, N
(2003)
Addressing Useless Test Data in Core-Based System-on-a-Chip Test.
IEEE Transactions on Computer-Aided Design, 22 (11), .
Abstract
This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and it leads to the trade-off between the test bus width and the volume of test data in multiple scan chains-based cores. Ultimately this trade-off influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed, which by dividing the wrapper scan chains into two or more partitions, and by exploiting automated test equipment memory management features reduces the useless memory. Extensive experimental results using ISCAS89 and ITC02 benchmark circuits are provided to analyze the implications of the number of wrapper scan chains in the partition, and the number of partitions on the proposed methodology.
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pgonciari_tcad03a.pdf
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More information
Published date: November 2003
Keywords:
Core-based test, core wrapper design, embedded core test, system-on-a-chip (SOC), useless test data, volume of test data
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 258531
URI: http://eprints.soton.ac.uk/id/eprint/258531
PURE UUID: e07dc399-a63e-491b-9102-e6c4226b9410
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Date deposited: 11 Nov 2003
Last modified: 14 Mar 2024 06:09
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Contributors
Author:
PT Gonciari
Author:
B Al-Hashimi
Author:
N Nicolici
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