Addressing Useless Test Data in Core-Based System-on-a-Chip Test

Gonciari, PT, Al-Hashimi, B and Nicolici, N (2003) Addressing Useless Test Data in Core-Based System-on-a-Chip Test IEEE Transactions on Computer-Aided Design, 22, (11), pp. 1568-1590.


[img] PDF pgonciari_tcad03a.pdf - Other
Download (228kB)


This paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and it leads to the trade-off between the test bus width and the volume of test data in multiple scan chains-based cores. Ultimately this trade-off influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed, which by dividing the wrapper scan chains into two or more partitions, and by exploiting automated test equipment memory management features reduces the useless memory. Extensive experimental results using ISCAS89 and ITC02 benchmark circuits are provided to analyze the implications of the number of wrapper scan chains in the partition, and the number of partitions on the proposed methodology.

Item Type: Article
Keywords: Core-based test, core wrapper design, embedded core test, system-on-a-chip (SOC), useless test data, volume of test data
Organisations: Electronic & Software Systems
ePrint ID: 258531
Date :
Date Event
November 2003Published
Date Deposited: 11 Nov 2003
Last Modified: 17 Apr 2017 22:42
Further Information:Google Scholar

Actions (login required)

View Item View Item