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Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems

Wu, D., Al-Hashimi, B. M. and Eles, P. (2003) Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems IEE Proceedings - Computers and Digital Techniques, 150, (5), pp. 262-273.

Record type: Article

Abstract

A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm based mapping with the DVS technique is examined and it is shown that further energy reduction can be achieved. The techniques are tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with an energy saving of up to 24%. Furthermore, it is shown that savings of up to 51% are achieved by considering DVS during the mapping optimisation. Finally, the impact of communications and communication link selection on the scheduling and mapping technique is investigated and results are reported.

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Published date: September 2003
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 258539
URI: http://eprints.soton.ac.uk/id/eprint/258539
PURE UUID: 49bf467f-fe66-4116-adf4-cc334bd26c7b

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Date deposited: 13 Nov 2003
Last modified: 24 Jul 2017 16:41

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Contributors

Author: D. Wu
Author: P. Eles

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