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Raised source/drain for 50nm MOSFETs: effect of epitaxy layer thickness on short channel effects

Raised source/drain for 50nm MOSFETs: effect of epitaxy layer thickness on short channel effects
Raised source/drain for 50nm MOSFETs: effect of epitaxy layer thickness on short channel effects
We present raised source/drain MOSFET devices with channel lengths down to 50nm. The raised source/drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre epitaxy process that eliminates the need for a pre epitaxy bake in hydrogen has been developed. In this study we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper we will show how short channel performance can be retrieved by adding the raised source/drain structures, and how increasing the thickness of these structures improves these parameters further
223-226
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Lloyd, N S
b37aa9e7-e478-40a8-9dbc-a72c63257cbe
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Ernst, T
c694f6be-2d8f-4cf7-97ba-3bee689ce741
Achard, S
d162175a-453d-49e8-99aa-45343647c858
Deleonibus, S
d68d89cd-e013-4bb6-9f4f-6075d9598068
Wang, Y
adc6c787-e577-46bf-bda7-740d56e7d554
Hemment, P L F
94618b9c-dba6-4cf6-b4d9-8770e7081532
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Lloyd, N S
b37aa9e7-e478-40a8-9dbc-a72c63257cbe
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Ernst, T
c694f6be-2d8f-4cf7-97ba-3bee689ce741
Achard, S
d162175a-453d-49e8-99aa-45343647c858
Deleonibus, S
d68d89cd-e013-4bb6-9f4f-6075d9598068
Wang, Y
adc6c787-e577-46bf-bda7-740d56e7d554
Hemment, P L F
94618b9c-dba6-4cf6-b4d9-8770e7081532

Waite, A M, Lloyd, N S, Ashburn, P, Evans, A G R, Ernst, T, Achard, S, Deleonibus, S, Wang, Y and Hemment, P L F (2003) Raised source/drain for 50nm MOSFETs: effect of epitaxy layer thickness on short channel effects. 33rd European Solid State Device Research Conference, Estoril, Portugal. 15 - 17 Sep 2003. pp. 223-226 .

Record type: Conference or Workshop Item (Other)

Abstract

We present raised source/drain MOSFET devices with channel lengths down to 50nm. The raised source/drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre epitaxy process that eliminates the need for a pre epitaxy bake in hydrogen has been developed. In this study we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper we will show how short channel performance can be retrieved by adding the raised source/drain structures, and how increasing the thickness of these structures improves these parameters further

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More information

Published date: 2003
Additional Information: Event Dates: 16-18 September 2003
Venue - Dates: 33rd European Solid State Device Research Conference, Estoril, Portugal, 2003-09-15 - 2003-09-17
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 258696
URI: http://eprints.soton.ac.uk/id/eprint/258696
PURE UUID: d118af8c-455a-4438-a6bb-935a4d03dd9f

Catalogue record

Date deposited: 23 Dec 2003
Last modified: 29 Jan 2020 15:33

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Contributors

Author: A M Waite
Author: N S Lloyd
Author: P Ashburn
Author: A G R Evans
Author: T Ernst
Author: S Achard
Author: S Deleonibus
Author: Y Wang
Author: P L F Hemment

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