Low temperature in-situ phosphorus doped single-crystal silicon emitters for application in SiGe HBTs
Low temperature in-situ phosphorus doped single-crystal silicon emitters for application in SiGe HBTs
SiGe HBTs require low temperature processing in order to minimise boron out-diffusion from the base region. In this paper, a novel technique of producing low temperature in-situ doped single-crystal silicon emitters for application in SiGe HBTs is presented. The single-crystal silicon was deposited at a temperature of 670C in a UHV-compatible LPCVD cluster tool. Gummel plots of the fabricated transistors show very ideal base characteristics. An ultra low emitter resistance of 6.6ohm.um2 was also obtained. The very low emitter resistance is due to a very low oxygen dose of 5.3E13cm-2 at the single-crystal silicon emitter / silicon substrate interface.
226-229
Abdul Rahim, A I
013c9698-3849-4ffb-8b15-59eff8259af5
Marsh, C D
b5482357-2e75-49f8-8217-72e1fde37c9f
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Booker, G R
1c5cd067-0dc6-4cd7-9e2c-9adf8ae291e9
2002
Abdul Rahim, A I
013c9698-3849-4ffb-8b15-59eff8259af5
Marsh, C D
b5482357-2e75-49f8-8217-72e1fde37c9f
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Booker, G R
1c5cd067-0dc6-4cd7-9e2c-9adf8ae291e9
Abdul Rahim, A I, Marsh, C D, Ashburn, P and Booker, G R
(2002)
Low temperature in-situ phosphorus doped single-crystal silicon emitters for application in SiGe HBTs.
IEEE International Conference on Semiconductor Electronics, Penang, Malaysia.
.
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Abstract
SiGe HBTs require low temperature processing in order to minimise boron out-diffusion from the base region. In this paper, a novel technique of producing low temperature in-situ doped single-crystal silicon emitters for application in SiGe HBTs is presented. The single-crystal silicon was deposited at a temperature of 670C in a UHV-compatible LPCVD cluster tool. Gummel plots of the fabricated transistors show very ideal base characteristics. An ultra low emitter resistance of 6.6ohm.um2 was also obtained. The very low emitter resistance is due to a very low oxygen dose of 5.3E13cm-2 at the single-crystal silicon emitter / silicon substrate interface.
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Published date: 2002
Venue - Dates:
IEEE International Conference on Semiconductor Electronics, Penang, Malaysia, 2002-01-01
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 258698
URI: http://eprints.soton.ac.uk/id/eprint/258698
PURE UUID: 18bc045d-8a54-4a4d-945d-bc8cd20a5fcf
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Date deposited: 23 Dec 2003
Last modified: 08 Jan 2022 14:43
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Contributors
Author:
A I Abdul Rahim
Author:
C D Marsh
Author:
G R Booker
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