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A FPGA Implementation of a Parallel Viterbi Decoder for Block Cyclic and Convolution Codes.

Record type: Conference or Workshop Item (Paper)

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from and processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes.

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Citation

Reeve, Jeffrey S and Amarasinghe, Kosala (2004) A FPGA Implementation of a Parallel Viterbi Decoder for Block Cyclic and Convolution Codes. At The IEEE International Conference on Communications. 20 - 24 Jun 2004.

More information

Published date: 2004
Additional Information: Event Dates: 20-24 June 2004
Venue - Dates: The IEEE International Conference on Communications, 2004-06-20 - 2004-06-24
Organisations: EEE

Identifiers

Local EPrints ID: 259027
URI: http://eprints.soton.ac.uk/id/eprint/259027
PURE UUID: 7d25319d-b612-4c65-8df4-8f86df08bf87

Catalogue record

Date deposited: 09 Mar 2004
Last modified: 18 Jul 2017 09:26

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Contributors

Author: Jeffrey S Reeve
Author: Kosala Amarasinghe

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