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A robust high speed serial PHY architecture with feed-forward correction clock and data recovery

A robust high speed serial PHY architecture with feed-forward correction clock and data recovery
A robust high speed serial PHY architecture with feed-forward correction clock and data recovery
This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-ATA PHY standards. To meet the primary design requirements of a sub-system that is very tolerant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A single fixed frequency low-jitter PLL serves the transmit and receive paths in both modes so that tracking and lock time issues are eliminated. A new oversampling CDR with a simple feed-forward error correction scheme is proposed which relaxes the requirements for the analog front-end as well as for the received signal quality. Measurements show that the error corrector can almost double the tolerance to incoming jitter and to DC offsets in the analog front-end. The design occupies less than 0.4 mm2 in 90 nm CMOS and consumes 75 mW
0018-9200
1914-1926
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf
Bugbee, Martin
2ff2f4d3-6c3a-4b98-b3ed-f245db449afc
Dobbs, Steve
09f4eed0-490c-4f24-b4cd-e27a1730204a
Wu, XinYan
3ca19297-59b5-4fae-afa8-67209844df77
Balmford, Richard
e9c82ff5-322c-4ce0-bdaf-5bcbea43e38a
Nuttgens, Jonah
92f0e559-252d-4095-a392-e3d5e4f6ff68
Kiami, Umer
84c09aba-ee4b-4002-87b3-e7700d7ee307
Clegg, Richard
994a2792-68a5-4a96-8530-d4a09128b4ad
den Besten, Gerrit
79021699-67cb-4011-893b-aaa1db9355a2
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf
Bugbee, Martin
2ff2f4d3-6c3a-4b98-b3ed-f245db449afc
Dobbs, Steve
09f4eed0-490c-4f24-b4cd-e27a1730204a
Wu, XinYan
3ca19297-59b5-4fae-afa8-67209844df77
Balmford, Richard
e9c82ff5-322c-4ce0-bdaf-5bcbea43e38a
Nuttgens, Jonah
92f0e559-252d-4095-a392-e3d5e4f6ff68
Kiami, Umer
84c09aba-ee4b-4002-87b3-e7700d7ee307
Clegg, Richard
994a2792-68a5-4a96-8530-d4a09128b4ad
den Besten, Gerrit
79021699-67cb-4011-893b-aaa1db9355a2

Redman-White, William, Bugbee, Martin, Dobbs, Steve, Wu, XinYan, Balmford, Richard, Nuttgens, Jonah, Kiami, Umer, Clegg, Richard and den Besten, Gerrit (2009) A robust high speed serial PHY architecture with feed-forward correction clock and data recovery. IEEE Journal of Solid State Circuits, 44 (7), 1914-1926. (doi:10.1109/JSSC.2009.2020230).

Record type: Article

Abstract

This paper describes a robust architecture for high speed serial links for embedded SoC applications, implemented to satisfy the 1.5 Gb/s and 3 Gb/s Serial-ATA PHY standards. To meet the primary design requirements of a sub-system that is very tolerant of device variability and is easy to port to smaller nanometre CMOS technologies, a minimum of precision analog functions are used. All digital functions are implemented in rail-to-rail CMOS with maximum use of synthesized library cells. A single fixed frequency low-jitter PLL serves the transmit and receive paths in both modes so that tracking and lock time issues are eliminated. A new oversampling CDR with a simple feed-forward error correction scheme is proposed which relaxes the requirements for the analog front-end as well as for the received signal quality. Measurements show that the error corrector can almost double the tolerance to incoming jitter and to DC offsets in the analog front-end. The design occupies less than 0.4 mm2 in 90 nm CMOS and consumes 75 mW

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Published date: July 2009
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 259242
URI: https://eprints.soton.ac.uk/id/eprint/259242
ISSN: 0018-9200
PURE UUID: f2ed92f9-d7f1-4feb-be4b-ba7ea5d149ab

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Date deposited: 15 Jul 2011 13:20
Last modified: 19 Jul 2019 22:40

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