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Synchronization Overhead in SOC Compressed Test

Gonciari, Paul Theo, Al-Hashimi, Bashir and Nicolici, Nicola (2005) Synchronization Overhead in SOC Compressed Test IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, (1), pp. 140-152.

Record type: Article

Abstract

Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-a-chip. This paper analyzes the sources of synchronization overhead and discusses the different trade-offs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.

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More information

Published date: January 2005
Keywords: SoC test, test data compression
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 259335
URI: http://eprints.soton.ac.uk/id/eprint/259335
PURE UUID: c69213b0-ef27-4478-be33-a2fc55dca5e2

Catalogue record

Date deposited: 10 May 2004
Last modified: 18 Jul 2017 09:24

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Contributors

Author: Paul Theo Gonciari
Author: Nicola Nicolici

University divisions

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