Leakage Power Analysis and Comparison of Deep Submicron Logic Gates


Merrett, Geoff and Al-Hashimi, Bashir M. (2004) Leakage Power Analysis and Comparison of Deep Submicron Logic Gates At IEEE 14th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2004), Greece. , pp. 198-207.

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Description/Abstract

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complementary pass-transistor logic. The XOR gate has been designed using a variety of additional circuit topologies, including double pass-transistor logic, differential cascade voltage switch logic and a gate designed specifically for low power. The investigation has been carried out with HSPICE using the Berkeley Predictive Technology Models (BTPM) for three deep submicron technologies (0.07µm, 0.1µm and 0.13µm).

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: September 2004
Venue - Dates: IEEE 14th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2004), Greece, 2004-09-01
Keywords: Leakage power, CMOS digital circuits, SPICE and DSM models
Organisations: Electronic & Software Systems
ePrint ID: 259481
Date :
Date Event
2004Published
Date Deposited: 22 Jun 2004
Last Modified: 23 Feb 2017 14:05
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/259481

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