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Leakage Power Analysis and Comparison of Deep Submicron Logic Gates

Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complementary pass-transistor logic. The XOR gate has been designed using a variety of additional circuit topologies, including double pass-transistor logic, differential cascade voltage switch logic and a gate designed specifically for low power. The investigation has been carried out with HSPICE using the Berkeley Predictive Technology Models (BTPM) for three deep submicron technologies (0.07µm, 0.1µm and 0.13µm).
Leakage power, CMOS digital circuits, SPICE and DSM models
198-207
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Merrett, Geoff and Al-Hashimi, Bashir M. (2004) Leakage Power Analysis and Comparison of Deep Submicron Logic Gates At IEEE 14th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2004), Greece. , pp. 198-207.

Record type: Conference or Workshop Item (Paper)

Abstract

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complementary pass-transistor logic. The XOR gate has been designed using a variety of additional circuit topologies, including double pass-transistor logic, differential cascade voltage switch logic and a gate designed specifically for low power. The investigation has been carried out with HSPICE using the Berkeley Predictive Technology Models (BTPM) for three deep submicron technologies (0.07µm, 0.1µm and 0.13µm).

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More information

Published date: 2004
Additional Information: Event Dates: September 2004
Venue - Dates: IEEE 14th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2004), Greece, 2004-09-01
Keywords: Leakage power, CMOS digital circuits, SPICE and DSM models
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 259481
URI: http://eprints.soton.ac.uk/id/eprint/259481
PURE UUID: 019c0cf3-dfb8-4773-87e8-2b62a27e8283
ORCID for Geoff Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 22 Jun 2004
Last modified: 18 Jul 2017 09:22

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Author: Geoff Merrett ORCID iD

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