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A stochastic neural architecture that exploits dynamically reconfigurable FPGAs

A stochastic neural architecture that exploits dynamically reconfigurable FPGAs
A stochastic neural architecture that exploits dynamically reconfigurable FPGAs
0818638907
202-211
IEEE Computer Society Press
Daalen, M.
f49a9ae4-bea1-4263-9f23-92835c39fa66
Jeavons, P.
bf271c75-e9a7-413c-8bd5-3f5d3ead0de1
Shawe-Taylor, John
b1931d97-fdd0-4bc1-89bc-ec01648e928b
Daalen, M.
f49a9ae4-bea1-4263-9f23-92835c39fa66
Jeavons, P.
bf271c75-e9a7-413c-8bd5-3f5d3ead0de1
Shawe-Taylor, John
b1931d97-fdd0-4bc1-89bc-ec01648e928b

Daalen, M., Jeavons, P. and Shawe-Taylor, John (1993) A stochastic neural architecture that exploits dynamically reconfigurable FPGAs. In Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines. IEEE Computer Society Press. pp. 202-211 .

Record type: Conference or Workshop Item (Paper)

Full text not available from this repository.

More information

Published date: 1993
Organisations: Electronics & Computer Science

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Local EPrints ID: 259700
URI: http://eprints.soton.ac.uk/id/eprint/259700
ISBN: 0818638907
PURE UUID: 0b0419f9-3a32-4823-929f-aea927b71d88

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Date deposited: 11 Aug 2004
Last modified: 16 May 2019 16:31

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