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Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems

Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems
Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems
In this paper, we propose a new technique for the combined voltagescaling of processors and communication links, taking into account dynamic as well as leakage power consumption. The voltage scaling technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. We also introduce a set of accurate communication models for the energy estimation of voltage scalable embedded systems. In particular, we demonstrate that voltage scaling of bus repeaters and dynamic adaption of the voltage swing on fat wires can significantly influence the system s energy consumption. Experimental results, conducted on numerous generated benchmarks and a real-life example, demonstrate that substantial energy savings can be achieved with the proposed techniques.
Low power system design, dynamic and leakage power reduction
361-367
Andrei, A
2cac74bb-156b-420f-b3d8-6dc93e6cd2f7
Schmitz, M
be2fb9dd-3dad-4531-85e7-56c998e80a5e
Eles, P
162d2495-cd8d-4222-8688-ea77a08bd1bf
Peng, Z
c83f0133-e9e5-4c93-ba0d-74396a9d80ca
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Andrei, A
2cac74bb-156b-420f-b3d8-6dc93e6cd2f7
Schmitz, M
be2fb9dd-3dad-4531-85e7-56c998e80a5e
Eles, P
162d2495-cd8d-4222-8688-ea77a08bd1bf
Peng, Z
c83f0133-e9e5-4c93-ba0d-74396a9d80ca
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Andrei, A, Schmitz, M, Eles, P, Peng, Z and Al-Hashimi, B.M. (2004) Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems. IEEE International Conference on Computer Aided Design (ICCAD). 07 - 11 Nov 2004. pp. 361-367 .

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper, we propose a new technique for the combined voltagescaling of processors and communication links, taking into account dynamic as well as leakage power consumption. The voltage scaling technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. We also introduce a set of accurate communication models for the energy estimation of voltage scalable embedded systems. In particular, we demonstrate that voltage scaling of bus repeaters and dynamic adaption of the voltage swing on fat wires can significantly influence the system s energy consumption. Experimental results, conducted on numerous generated benchmarks and a real-life example, demonstrate that substantial energy savings can be achieved with the proposed techniques.

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More information

Published date: 2004
Additional Information: Event Dates: Nov 7-11, 2004
Venue - Dates: IEEE International Conference on Computer Aided Design (ICCAD), 2004-11-07 - 2004-11-11
Keywords: Low power system design, dynamic and leakage power reduction
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 259743
URI: https://eprints.soton.ac.uk/id/eprint/259743
PURE UUID: 1888d82c-e116-45fc-bb96-9837cc879c23

Catalogue record

Date deposited: 12 Aug 2004
Last modified: 26 Feb 2019 17:32

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