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Low Power Multi-Gigahertz Divider Architectures in SOI CMOS Employing Series Current Reuse

Low Power Multi-Gigahertz Divider Architectures in SOI CMOS Employing Series Current Reuse
Low Power Multi-Gigahertz Divider Architectures in SOI CMOS Employing Series Current Reuse
Mistry, K.
6cc6ca40-90ac-4342-8025-6c03da23c4e2
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Benson, J.
594e14de-a2a3-4e8e-9f74-947c50735671
D'Halleweyn, N.
99ae9eea-2e92-4993-8f21-ab2f5133a00b
Mistry, K.
6cc6ca40-90ac-4342-8025-6c03da23c4e2
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Benson, J.
594e14de-a2a3-4e8e-9f74-947c50735671
D'Halleweyn, N.
99ae9eea-2e92-4993-8f21-ab2f5133a00b

Mistry, K., Redman-White, W., Benson, J. and D'Halleweyn, N. (2001) Low Power Multi-Gigahertz Divider Architectures in SOI CMOS Employing Series Current Reuse. Proceedings of the European Conference on Circuit theory and Design, Finland.

Record type: Conference or Workshop Item (Paper)

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More information

Published date: 2001
Additional Information: Event Dates: August 2001
Venue - Dates: Proceedings of the European Conference on Circuit theory and Design, Finland, 2001-08-01
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 259896
URI: https://eprints.soton.ac.uk/id/eprint/259896
PURE UUID: 1ddb652a-0985-40b5-87f6-eb697058fa6f

Catalogue record

Date deposited: 03 Sep 2004
Last modified: 18 Jul 2017 09:18

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