Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction
Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction
Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive body bias (ABB) techniques achieve the highest reduction in embedded systems energy dissipation [1]. In this paper we show that it is possible to produce comparable energy saving to that obtained using combined DVS and ABB techniques but with reduced hardware cost achieved by employing processing elements (PEs) with separate DVS or ABB capability. A co-synthesis methodology which is aware of tasks’ power-composition profile (the ratio of the dynamic power to the leakage power) is presented. The methodology selects voltage scaling capabilities (DVS, ABB, or combined DVS and ABB) for the PEs, maps, schedules, and voltage scales applications given as task graphs with timing constraints, aiming to dynamic and leakage energy reduction at low hardware cost. We conduct detailed experiments, including a real-life example, to demonstrate the effectiveness of our methodology. We demonstrate that it is possible to produce designs that contain PEs with only DVS or ABB technique but have energy dissipation that are only 4.4% higher when compared with the same designs that employ PEs with combined DVS and ABB capabilities.
Wu, Dong
0929d522-75bc-46f5-887e-027662ea4ebc
Al-Hashimi, Bashir M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
2004
Wu, Dong
0929d522-75bc-46f5-887e-027662ea4ebc
Al-Hashimi, Bashir M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Wu, Dong, Al-Hashimi, Bashir M and Eles, Petru
(2004)
Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction.
System-On-Chip Design, Test and Technology, Loughborough, United Kingdom.
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Conference or Workshop Item
(Paper)
Abstract
Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive body bias (ABB) techniques achieve the highest reduction in embedded systems energy dissipation [1]. In this paper we show that it is possible to produce comparable energy saving to that obtained using combined DVS and ABB techniques but with reduced hardware cost achieved by employing processing elements (PEs) with separate DVS or ABB capability. A co-synthesis methodology which is aware of tasks’ power-composition profile (the ratio of the dynamic power to the leakage power) is presented. The methodology selects voltage scaling capabilities (DVS, ABB, or combined DVS and ABB) for the PEs, maps, schedules, and voltage scales applications given as task graphs with timing constraints, aiming to dynamic and leakage energy reduction at low hardware cost. We conduct detailed experiments, including a real-life example, to demonstrate the effectiveness of our methodology. We demonstrate that it is possible to produce designs that contain PEs with only DVS or ABB technique but have energy dissipation that are only 4.4% higher when compared with the same designs that employ PEs with combined DVS and ABB capabilities.
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Published date: 2004
Additional Information:
Event Dates: September 2004
Venue - Dates:
System-On-Chip Design, Test and Technology, Loughborough, United Kingdom, 2004-09-01
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 259899
URI: http://eprints.soton.ac.uk/id/eprint/259899
PURE UUID: ff13dcc6-bda4-49cf-9827-11403b5253d9
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Date deposited: 02 Sep 2004
Last modified: 14 Mar 2024 06:29
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Contributors
Author:
Dong Wu
Author:
Bashir M Al-Hashimi
Author:
Petru Eles
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