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Iterative Schedule Optimization for Voltage Scalable Distributed Embedded Systems

Iterative Schedule Optimization for Voltage Scalable Distributed Embedded Systems
Iterative Schedule Optimization for Voltage Scalable Distributed Embedded Systems
We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs).To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.
182-217
Schmitz, Marcus T
824cce4a-6528-4bd1-8357-3cfa637d20f1
Al-Hashimi, Bashir M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Schmitz, Marcus T
824cce4a-6528-4bd1-8357-3cfa637d20f1
Al-Hashimi, Bashir M
0b29c671-a6d2-459c-af68-c4614dce3b5d
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f

Schmitz, Marcus T, Al-Hashimi, Bashir M and Eles, Petru (2004) Iterative Schedule Optimization for Voltage Scalable Distributed Embedded Systems. ACM Transactions on Embedded Computing Systems, 3 (1), 182-217.

Record type: Article

Abstract

We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs).To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

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Published date: February 2004
Organisations: Electronic & Software Systems

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Local EPrints ID: 260132
URI: https://eprints.soton.ac.uk/id/eprint/260132
PURE UUID: 4d116f6c-5595-4f9e-aceb-d6825bc6e75c

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Date deposited: 23 Nov 2004
Last modified: 16 Jul 2019 22:51

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