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Rapid generation of thermal-safe test schedules

Rosinger, Paul, Al-Hashimi, Bashir and Chakrabarty, Krishnendu (2005) Rapid generation of thermal-safe test schedules At Design Automation and Test in Europe (DATE), Germany. 07 - 11 Mar 2005.

Record type: Conference or Workshop Item (Paper)


Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have been recently proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.

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Published date: 2005
Additional Information: Event Dates: 7-11 March 2005
Venue - Dates: Design Automation and Test in Europe (DATE), Germany, 2005-03-07 - 2005-03-11
Keywords: DFT, test, low power
Organisations: Electronic & Software Systems


Local EPrints ID: 260180
PURE UUID: 7c973d0f-9de1-4129-a880-70706ccd90ec

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Date deposited: 07 Dec 2004
Last modified: 18 Jul 2017 09:15

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Author: Paul Rosinger
Author: Krishnendu Chakrabarty

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