Rosinger, Paul, Al-Hashimi, Bashir and Chakrabarty, Krishnendu
Rapid generation of thermal-safe test schedules
At Design Automation and Test in Europe (DATE), Germany.
07 - 11 Mar 2005.
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have been recently proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.
Conference or Workshop Item
||Event Dates: 7-11 March 2005
|Venue - Dates:
||Design Automation and Test in Europe (DATE), Germany, 2005-03-07 - 2005-03-11
||DFT, test, low power
||Electronic & Software Systems
||07 Dec 2004
||17 Apr 2017 22:17
|Further Information:||Google Scholar|
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