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Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique

Gaur, MS and Zwolinski, M (2004) Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique At 17th International Conference on VLSI Design (VLSID’04), India. , pp. 901-906.

Record type: Conference or Workshop Item (Paper)


Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-Transfer- Level (RTL) data path generated from a behavioural description to make more testable. Although it can be argued that good results have been obtained with such approaches, we must keep in mind that with the emergence of commercial behavioural synthesis tools it is difficult for the designer to understand an automatically generated structural RTL description. With the ever increasing complexity and pressure to shorten time to market, test synthesis must not be dissociated from design synthesis. This paper shows that it is possible to generate optimised self-testable RTL when addressed at the highest level of abstraction ie., behavioural description. This is achieved by developing a novel and accurate Built-In Self-Test (BIST) resource estimation technique based on exploitation of certain characteristics of the controller of the design.

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Published date: 2004
Additional Information: Event Dates: January 2004
Venue - Dates: 17th International Conference on VLSI Design (VLSID’04), India, 2004-01-01
Organisations: EEE


Local EPrints ID: 260385
PURE UUID: 7eaab5c1-2a39-426a-b515-65bbab2ccbef
ORCID for M Zwolinski: ORCID iD

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Date deposited: 27 Jan 2005
Last modified: 18 Jul 2017 09:13

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Author: MS Gaur
Author: M Zwolinski ORCID iD

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