Concurrent analogue fault simulation, the equation formulation aspect

Abstract

Fault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well-established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault-free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated.

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ORCID for M Zwolinski: orcid.org/0000-0002-2230-625X

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