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Concurrent analogue fault simulation, the equation formulation aspect

Concurrent analogue fault simulation, the equation formulation aspect
Concurrent analogue fault simulation, the equation formulation aspect
Fault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well-established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault-free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated.
analogue fault simulation, analogue and mixed-signal testing, fault dictionaries, fault modelling
0098-9886
487-507
Litovski, VB
e0946185-294c-4f6f-96de-4283c1c56c0a
Litovski, IV
f2baf79b-a168-40cf-8588-21cc52c0f7ce
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Litovski, VB
e0946185-294c-4f6f-96de-4283c1c56c0a
Litovski, IV
f2baf79b-a168-40cf-8588-21cc52c0f7ce
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Litovski, VB, Litovski, IV and Zwolinski, M (2004) Concurrent analogue fault simulation, the equation formulation aspect International Journal of Circuit Theory and Applications, 32, (6), pp. 487-507.

Record type: Article

Abstract

Fault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well-established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault-free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated.

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Published date: December 2004
Additional Information: Uncorrected proof
Keywords: analogue fault simulation, analogue and mixed-signal testing, fault dictionaries, fault modelling
Organisations: EEE

Identifiers

Local EPrints ID: 260386
URI: http://eprints.soton.ac.uk/id/eprint/260386
ISSN: 0098-9886
PURE UUID: 362181b0-b90a-4537-aed4-4ea1017e3eff
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 27 Jan 2005
Last modified: 24 Jul 2017 16:41

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Contributors

Author: VB Litovski
Author: IV Litovski
Author: M Zwolinski ORCID iD

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