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Behavioural synthesis utilising dynamic memory constructs

Behavioural synthesis utilising dynamic memory constructs
Behavioural synthesis utilising dynamic memory constructs
Behavioural synthesis is the process whereby the description of a system behaviour is automatically translated into a physical implementation of that system. An essential prerequisite of this process is a language in which to express the design. Traditionally, hardware description languages (HDLs) are used for this, but there is currently much interest in the idea of coercing conventional software languages to do the same job (SystemC is the most prominent example of this). The goal of the research described is to increase the synthesisable description space to support the description of systems utilising dynamic allocation. VHDL supports the concepts of dynamic allocation, and is used as the entry language for the system, although without loss of validity SystemC could have been used. How the structures conventionally associated with dynamic description are implemented and supported is described together with a heap management subsystem that is both space and speed-efficient and which communicates with the user's design via an automatically generated interface.
1350-2387
252-264
Milton, DJD
29b00dde-4201-47c6-8a47-5bf327310a3c
Brown, AD
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wilson, PR
8a65c092-c197-4f43-b8fc-e12977783cb3
Milton, DJD
29b00dde-4201-47c6-8a47-5bf327310a3c
Brown, AD
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Wilson, PR
8a65c092-c197-4f43-b8fc-e12977783cb3

Milton, DJD, Brown, AD, Zwolinski, M and Wilson, PR (2004) Behavioural synthesis utilising dynamic memory constructs. IEE Proceedings - Computers and Digital Techniques, 151 (3), 252-264.

Record type: Article

Abstract

Behavioural synthesis is the process whereby the description of a system behaviour is automatically translated into a physical implementation of that system. An essential prerequisite of this process is a language in which to express the design. Traditionally, hardware description languages (HDLs) are used for this, but there is currently much interest in the idea of coercing conventional software languages to do the same job (SystemC is the most prominent example of this). The goal of the research described is to increase the synthesisable description space to support the description of systems utilising dynamic allocation. VHDL supports the concepts of dynamic allocation, and is used as the entry language for the system, although without loss of validity SystemC could have been used. How the structures conventionally associated with dynamic description are implemented and supported is described together with a heap management subsystem that is both space and speed-efficient and which communicates with the user's design via an automatically generated interface.

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More information

Published date: May 2004
Organisations: EEE

Identifiers

Local EPrints ID: 260390
URI: http://eprints.soton.ac.uk/id/eprint/260390
ISSN: 1350-2387
PURE UUID: 21185490-6e0d-4f51-9ce9-daba0aeb0fa9
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 27 Jan 2005
Last modified: 15 Mar 2024 02:39

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Contributors

Author: DJD Milton
Author: AD Brown
Author: M Zwolinski ORCID iD
Author: PR Wilson

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