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Behavioural modelling of analogue faults in VHDL-AMS - A case study

Record type: Conference or Workshop Item (Paper)

Analogue fault simulation is needed to evaluate the quality of tests, but is very computationally intensive. Behavioural simulation is more abstract and thus faster than fault simulation. Using a phase-locked loop as a case study, we show how behavioural fault models can be derived from transistor-level fault simulations and that faulty behaviour can be accurately modeled.

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Citation

Brown, AD and Zwolinski, M (2004) Behavioural modelling of analogue faults in VHDL-AMS - A case study At 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Canada. 23 - 26 May 2004. , V632-V635.

More information

Published date: 2004
Additional Information: Event Dates: MAY 23-26, 2004
Venue - Dates: 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Canada, 2004-05-23 - 2004-05-26
Keywords: fault simulation hardware description languages integrated circuit modelling mixed analogue-digital integrated circuits phase locked loops VHDL-AMS analogue fault simulation behavioural analogue fault modelling behavioural fault models behavioural simulation faulty behaviour modelling intensive computation phase-locked loop transistor-level fault simulation
Organisations: EEE

Identifiers

Local EPrints ID: 260391
URI: http://eprints.soton.ac.uk/id/eprint/260391
PURE UUID: 41a0386c-11a1-4808-8a29-b3e6026f0db8
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 27 Jan 2005
Last modified: 18 Jul 2017 09:13

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Contributors

Author: AD Brown
Author: M Zwolinski ORCID iD

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