The University of Southampton
University of Southampton Institutional Repository

Behavioural Modeling and Simulation of a Switched-Current Phase Locked Loop

Wilson, Peter R. and Wilcock, Reuben (2005) Behavioural Modeling and Simulation of a Switched-Current Phase Locked Loop At ISCAS 2005, Japan.

Record type: Conference or Workshop Item (Paper)


Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Further recent advances indicate that adopting a switched current architecture can lead to equivalent performance but with a significantly reduced area compared to switched capacitor structures. While this is useful in itself, the use of behavioural modeling and simulation at a structural and building block level has allowed architectural exploration and evaluation to be carried out on novel topologies based on this approach. The result is an integrated design flow that uses behavioural models to test the performance of the circuit, leading directly to a synthesized structural model that can be verified using a common design platform. This has the obvious benefit of reducing the full custom analog design effort required when developing topologies and building blocks for new processes. In this paper we describe the design approach of a Phase Locked Loop (PLL) based on a novel Switched-Current (SI) architecture using behavioural models written in VHDL-AMS. Simulations demonstrate the performance of the design at a high level and are used to optimize the behaviour of the loop response with regard to design specifications. The modeling approach is explained, from the basic building blocks used in the SI methodology through to more abstract models of the system architecture. The advantage of using behavioural models is highlighted with the ability to carry out parametric analysis and statistical analysis to investigate tolerances, adherence to specifications and parameter variations. The resulting simulations are consistent with transistor level simulation results, but several orders of magnitude faster. The resulting design achieves a performance that is comparable with designs using current techniques but with significantly reduced area.

Full text not available from this repository.

More information

Published date: 2005
Additional Information: Event Dates: May 2005
Venue - Dates: ISCAS 2005, Japan, 2005-05-01
Organisations: EEE


Local EPrints ID: 260403
PURE UUID: 87dcf51f-703a-41eb-9c29-89465f605d7c

Catalogue record

Date deposited: 28 Jan 2005
Last modified: 18 Jul 2017 09:13

Export record


Author: Peter R. Wilson
Author: Reuben Wilcock

University divisions

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton:

ePrints Soton supports OAI 2.0 with a base URL of

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.