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A Novel Switch-Current Phase Locked Loop

Wilcock, Reuben, Wilson, Peter R. and Al-Hashimi, Bashir (2005) A Novel Switch-Current Phase Locked Loop At ISCAS 2005, Japan.

Record type: Conference or Workshop Item (Poster)

Abstract

This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35?m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

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More information

Published date: 2005
Additional Information: Event Dates: May 2005
Venue - Dates: ISCAS 2005, Japan, 2005-05-01
Organisations: Electronic & Software Systems, EEE

Identifiers

Local EPrints ID: 260404
URI: http://eprints.soton.ac.uk/id/eprint/260404
PURE UUID: a2964839-0c0b-4edd-8f8e-74e094475880

Catalogue record

Date deposited: 28 Jan 2005
Last modified: 18 Jul 2017 09:13

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Contributors

Author: Reuben Wilcock
Author: Peter R. Wilson

University divisions

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