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Issues in the design of a logic simulator: an improved caching technique for event-queue management

Brown, AD, Nichols, KG and Zwolinski, M (1995) Issues in the design of a logic simulator: an improved caching technique for event-queue management IEE Proceedings - Circuits, Devices and Systems, 142, (5), pp. 293-298.

Record type: Article

Abstract

The paper describes certain issues relevant to the development of a logic simulation engine, designed to be incorporated into a mixed-signal simulator. Usually, the rate-limiting process in any mixed-signal simulation is the analogue processing but, for systems with a significant asymmetry between logic and analogue components, the efficiency of the logic engine can obviously become important. A technique is reported for improving both the space and time complexity of the logic engine: a method of event-queue searching using multiple cache pointers. Experimental results show that about five cache pointers provide the optimum efficiency gain from this technique. Finally, problems of event-queue management are reviewed, with particular reference to the situation where simulation time is represented by a real number, as it must be in a mixed-signal environment.

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More information

Published date: October 1995
Keywords: LOGIC SIMULATORS, EVENT QUEUE MANAGEMENT
Organisations: EEE

Identifiers

Local EPrints ID: 260437
URI: http://eprints.soton.ac.uk/id/eprint/260437
ISSN: 1350-2409
PURE UUID: b38a40cb-d321-48e9-9c8c-bd32e62cf343
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 03 Feb 2005
Last modified: 18 Jul 2017 09:13

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Contributors

Author: AD Brown
Author: KG Nichols
Author: M Zwolinski ORCID iD

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