A Programmable Time Measurement Architecture for Embedded Memory Characterization
A Programmable Time Measurement Architecture for Embedded Memory Characterization
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry [1] or circuit duplication [2]. This is achieved by the use of Time-to-Digital Conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering Time-to-Voltage Converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18?m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110?m x 75?m.
128-133
Collins, Matthew
5afb2125-3382-4c0b-958e-37efe20bc5a1
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Ross, Neil
035ecb5f-c3c1-4f13-87d9-3df8d26b4a56
2005
Collins, Matthew
5afb2125-3382-4c0b-958e-37efe20bc5a1
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Ross, Neil
035ecb5f-c3c1-4f13-87d9-3df8d26b4a56
Collins, Matthew, Al-Hashimi, Bashir and Ross, Neil
(2005)
A Programmable Time Measurement Architecture for Embedded Memory Characterization.
10th IEEE European Test Symposium (ETS'05), Tallinn, Estonia.
22 - 25 May 2005.
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry [1] or circuit duplication [2]. This is achieved by the use of Time-to-Digital Conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering Time-to-Voltage Converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18?m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110?m x 75?m.
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collinsm_timemeasurement.pdf
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Published date: 2005
Additional Information:
Event Dates: 22-25 May
Venue - Dates:
10th IEEE European Test Symposium (ETS'05), Tallinn, Estonia, 2005-05-22 - 2005-05-25
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 260640
URI: http://eprints.soton.ac.uk/id/eprint/260640
PURE UUID: d2b38aa9-d8e5-49c7-9a7f-5e4746721048
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Date deposited: 01 Jun 2005
Last modified: 14 Mar 2024 06:40
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Contributors
Author:
Matthew Collins
Author:
Bashir Al-Hashimi
Author:
Neil Ross
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