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A Programmable Time Measurement Architecture for Embedded Memory Characterization

Record type: Conference or Workshop Item (Paper)

This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry [1] or circuit duplication [2]. This is achieved by the use of Time-to-Digital Conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering Time-to-Voltage Converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18?m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110?m x 75?m.

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Citation

Collins, Matthew, Al-Hashimi, Bashir and Ross, Neil (2005) A Programmable Time Measurement Architecture for Embedded Memory Characterization At 10th IEEE European Test Symposium (ETS'05), Estonia. 22 - 25 May 2005. , pp. 128-133.

More information

Published date: 2005
Additional Information: Event Dates: 22-25 May
Venue - Dates: 10th IEEE European Test Symposium (ETS'05), Estonia, 2005-05-22 - 2005-05-25
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 260640
URI: http://eprints.soton.ac.uk/id/eprint/260640
PURE UUID: d2b38aa9-d8e5-49c7-9a7f-5e4746721048

Catalogue record

Date deposited: 01 Jun 2005
Last modified: 17 Apr 2017 22:12

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Contributors

Author: Matthew Collins
Author: Neil Ross

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