Pradhan, Dhiraj K., Abadir, Magdy S. and Varea, Mauricio (2005) Recent Advances in Verification, Equivalence Checking and SAT-Solvers. 18th International Conference on VLSI Design, Kolkata, India. 03 - 07 Jan 2005. p. 14 .
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Published date: 2005
Additional Information:
Event Dates: 3-7 January 2005
Venue - Dates:
18th International Conference on VLSI Design, Kolkata, India, 2005-01-03 - 2005-01-07
Organisations:
Electronics & Computer Science
Identifiers
Local EPrints ID: 260652
URI: http://eprints.soton.ac.uk/id/eprint/260652
ISBN: 0-7695-2264-5
PURE UUID: dc89d8de-d1f5-49f5-82bf-11f77efbd283
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Date deposited: 07 Mar 2005
Last modified: 10 Dec 2021 21:12
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Contributors
Author:
Dhiraj K. Pradhan
Author:
Magdy S. Abadir
Author:
Mauricio Varea
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