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Thermal oxidation of strained Si/SiGe: impact of surface morphology and effect on MOS devices

Record type: Article

The performance of surface channel MOS devices depends on gate oxide interface quality. Carrier transport is enhanced in strained Si, thus its use for MOSFET channels can increase device performance. Thermal oxidation produces the highest quality Si02. This paper compares thermal oxidation of strained Si with unstrained Si. Strained Si is achieved by epitaxial growth on relazed SiGe. The impact of large-scale cross-hatching roughness inherent in relaxed SiGe alloys on strained Si oxidation is investigated. The nanoscale oxide interface roughness and oxidation rate of strained Si are found to correlate with the undulating cross-hatch period, increasing and decreasing, respectively, with the degree of surface vicinality. Further, analysis suggests strained Si oxidation kinetics arise primarily from local variations in the SiGe substrate orientation due to cross-hatching, rather than strain. Devices fabricated on relatively smooth SiGe material exhibit electrical performance enhancements exceeding 75% compared with devices fabricated on material with severe cross-hatching. Likely causes for the dependence of strained Si oxidation kinetics on surface morphology and the impact on MOS devices are discussed. The enhanced performance of strained Si/SiGe MOSFETs over Si control devices with equivalent oxide interface roughness is also presented. Strained Si devices exhibit mobility gains greater than 100% and significant increases in transconductance compared with control devices. (C) 2003 Elsevier B.V. All rights reserved.

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Citation

Olsen, S.H., O'Neill, A.G., Norris, D.J., Cullis, A.G., Bull, S.J., Chattopadhyay, S., Kwa, K.S.K., Driscoll, L.S., Waite, A.M., Tang, Y.T. and Evans, A.G.R. (2004) Thermal oxidation of strained Si/SiGe: impact of surface morphology and effect on MOS devices Materials Science and Engineering: B, 109, (1-3), pp. 78-84.

More information

Published date: June 2004
Keywords: strained Si, SiGe, MOSFET, virtual substrate, oxidation, surface roughness
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260884
URI: http://eprints.soton.ac.uk/id/eprint/260884
ISSN: 0921-5107
PURE UUID: 7ceac910-c51f-4fe2-ba1c-715e570c8a49

Catalogue record

Date deposited: 17 May 2005
Last modified: 18 Jul 2017 09:08

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Contributors

Author: S.H. Olsen
Author: A.G. O'Neill
Author: D.J. Norris
Author: A.G. Cullis
Author: S.J. Bull
Author: S. Chattopadhyay
Author: K.S.K. Kwa
Author: L.S. Driscoll
Author: A.M. Waite
Author: Y.T. Tang
Author: A.G.R. Evans

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