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Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling

Record type: Conference or Workshop Item (Paper)

Recently we have shown how hot-spots during test can be avoided without unnecessarily increasing the testing time by using a thermal-safe test scheduling approach. In this work, we investigate the impact of scan shift frequency scaling on the thermal-safe test scheduling performance and propose an algorithm which embeds shift frequency scaling into the test scheduling process. Experimental results show that this approach offers shorter overall testing times and significantly improved ability of meeting tight thermal constraints when compared to existing thermal-safe test scheduling approach based on a fixed scan shift frequency.

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Citation

Tafaj, Enkelejda, Rosinger, Paul, Al-Hashimi, Bashir and Chakrabarty, Krisnendu (2005) Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling At International Symposium on Defect and Fault Tolerance in VLSI Systems. 03 - 05 Oct 2005.

More information

Published date: 2005
Additional Information: Event Dates: 3-5 October
Venue - Dates: International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005-10-03 - 2005-10-05
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 261102
URI: http://eprints.soton.ac.uk/id/eprint/261102
PURE UUID: 44e104ac-514b-47c9-9cc5-0d65a1704a1e

Catalogue record

Date deposited: 02 Aug 2005
Last modified: 18 Jul 2017 09:05

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Contributors

Author: Enkelejda Tafaj
Author: Paul Rosinger
Author: Krisnendu Chakrabarty

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