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Thermal-Safe Test Scheduling for Core-Based System-on-a-Chip Integrated Circuits

Record type: Article

Overheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC) integrated circuits. Several power-constrained test scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the non-uniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test scheduling approach that is able to produce short test schedules and guarantee thermal-safety at the same time. Two thermal-safe test scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test scheduling algorithm may not be feasible. Based on a low-complexity test session thermal cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm.

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Citation

Rosinger, Paul, Al-Hashimi, Bashir and Chakrabarty, Krishnendu (2005) Thermal-Safe Test Scheduling for Core-Based System-on-a-Chip Integrated Circuits IEEE Transactions on Computer Aided Design, 25, (11), pp. 2502-2512.

More information

Published date: November 2005
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 261582
URI: http://eprints.soton.ac.uk/id/eprint/261582
PURE UUID: f4020f6f-254c-40cb-801b-e6d27acba444

Catalogue record

Date deposited: 24 Nov 2005
Last modified: 18 Jul 2017 09:01

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Contributors

Author: Paul Rosinger
Author: Krishnendu Chakrabarty

University divisions

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