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Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity
Minimizing Test Power in SRAM through Reduction of Pre-charge Activity
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations.
Test, SRAM, low power, DfT, March Test, Pre-charge
DILILLO, L.
ab9fd69f-6112-47c5-9bd6-7905f369a684
ROSINGER, P.
c2003b82-b630-45ab-b8b0-c54054f7db69
AL-HASHIMI, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
GIRARD, P.
c8beda40-0a01-42d9-9631-d7c60aa6d3c2
DILILLO, L.
ab9fd69f-6112-47c5-9bd6-7905f369a684
ROSINGER, P.
c2003b82-b630-45ab-b8b0-c54054f7db69
AL-HASHIMI, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
GIRARD, P.
c8beda40-0a01-42d9-9631-d7c60aa6d3c2

DILILLO, L., ROSINGER, P., AL-HASHIMI, B. M. and GIRARD, P. (2006) Minimizing Test Power in SRAM through Reduction of Pre-charge Activity. DATE - Design Automation and Test in Europe, Germany. 06 - 10 Mar 2006.

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations.

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More information

Published date: 2006
Additional Information: Event Dates: 6-10 March 2006
Venue - Dates: DATE - Design Automation and Test in Europe, Germany, 2006-03-06 - 2006-03-10
Keywords: Test, SRAM, low power, DfT, March Test, Pre-charge
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 261644
URI: http://eprints.soton.ac.uk/id/eprint/261644
PURE UUID: d5296a94-dd0e-4132-8602-1cc2cb6e572d

Catalogue record

Date deposited: 13 Dec 2005
Last modified: 25 Nov 2019 21:05

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