HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope
HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope
A new methodology is presented to assure numerically reliable integration of the magnetisation slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two HDL implementations of the technique are presented, one in SystemC and the other in VHDL-AMS. The new model uses timeless discretisation of the magnetisation slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetisation slope is carried out by the model itself rather than by the underlying analogue solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops.
CAD, mixed-signal, HDL, VHDL-AMS, SystemC
AL-Junaid, Hessa
e957dd9f-e025-4a69-b699-ac9248515853
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a
2006
AL-Junaid, Hessa
e957dd9f-e025-4a69-b699-ac9248515853
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a
AL-Junaid, Hessa and Kazmierski, Tom
(2006)
HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope.
Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany.
06 - 10 Mar 2006.
Record type:
Conference or Workshop Item
(Paper)
Abstract
A new methodology is presented to assure numerically reliable integration of the magnetisation slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two HDL implementations of the technique are presented, one in SystemC and the other in VHDL-AMS. The new model uses timeless discretisation of the magnetisation slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetisation slope is carried out by the model itself rather than by the underlying analogue solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops.
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06B_4_157.pdf.pdf
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Published date: 2006
Additional Information:
Event Dates: 6-10 March
Venue - Dates:
Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany, 2006-03-06 - 2006-03-10
Keywords:
CAD, mixed-signal, HDL, VHDL-AMS, SystemC
Organisations:
EEE
Identifiers
Local EPrints ID: 262029
URI: http://eprints.soton.ac.uk/id/eprint/262029
PURE UUID: 4d991abd-a029-4f29-823b-734aaf5a43dc
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Date deposited: 01 Mar 2006
Last modified: 14 Mar 2024 07:03
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Contributors
Author:
Hessa AL-Junaid
Author:
Tom Kazmierski
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