Riepe, M. A., Marques-Silva, J. P., Sakallah, K. A. and Brown, R. B. (1996) Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Transactions on VLSI Systems, 4 (1), 113-129.
Record type:
Article
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Published date: March 1996
Organisations:
Electronics & Computer Science
Identifiers
Local EPrints ID: 262044
URI: http://eprints.soton.ac.uk/id/eprint/262044
PURE UUID: bcced59b-0aa1-4f87-8ae9-09e3d2430fa2
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Date deposited: 02 Mar 2006
Last modified: 14 Mar 2024 07:04
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Contributors
Author:
M. A. Riepe
Author:
J. P. Marques-Silva
Author:
K. A. Sakallah
Author:
R. B. Brown
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