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Enhancing delay fault coverage through low power segmented scan

Zhang, Zhuo, M. Reddy, Sudhakar, Pomeranz, Irith, Rajski, Janusz and M. Al-Hashimi, Bashir (2006) Enhancing delay fault coverage through low power segmented scan In Eleventh IEEE European Test Symposium, 2006. ETS '06. IEEE.. (doi:10.1109/ETS.2006.18).

Record type: Conference or Workshop Item (Paper)

Abstract

Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%.

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Published date: May 2006
Keywords: Low power test, DFT, delay test

Identifiers

Local EPrints ID: 262097
URI: http://eprints.soton.ac.uk/id/eprint/262097
PURE UUID: e0de216f-113c-44db-bb5e-7745d934713a

Catalogue record

Date deposited: 21 Mar 2006
Last modified: 17 Aug 2017 16:30

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Contributors

Author: Zhuo Zhang
Author: Sudhakar M. Reddy
Author: Irith Pomeranz
Author: Janusz Rajski

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