Onai, T, Tsujikawa, S, Uchino, T, Tsuchiya, R, Ohnishi, K, Fukuda, H, Hisamoto, D, Yamamoto, N, Yugami, J, Ichinose, K and Ootsuka, F (1999) 0.1-μm CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate system. IEDM Tech. Digest, 937.
Record type:
Article
This record has no associated files available for download.
More information
Published date: 1999
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 262167
URI: http://eprints.soton.ac.uk/id/eprint/262167
PURE UUID: e4987d6d-06bb-425c-84aa-d4399dbb6191
Catalogue record
Date deposited: 27 Mar 2006
Last modified: 08 Jan 2022 05:46
Export record
Contributors
Author:
T Onai
Author:
S Tsujikawa
Author:
T Uchino
Author:
R Tsuchiya
Author:
K Ohnishi
Author:
H Fukuda
Author:
D Hisamoto
Author:
N Yamamoto
Author:
J Yugami
Author:
K Ichinose
Author:
F Ootsuka
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.