A parallel Viterbi decoder for block cyclic and convolution codes
A parallel Viterbi decoder for block cyclic and convolution codes
We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes.
Viterbi decoding, BCH codes, Field Programmable Gate Array, parallel algorithms
273-278
Reeve, Jeffrey
dd909010-7d44-44ea-83fe-a09e4d492618
Amarasinghe, Kosala
8df42214-345d-4403-ab07-dbd9765e0469
2006
Reeve, Jeffrey
dd909010-7d44-44ea-83fe-a09e4d492618
Amarasinghe, Kosala
8df42214-345d-4403-ab07-dbd9765e0469
Reeve, Jeffrey and Amarasinghe, Kosala
(2006)
A parallel Viterbi decoder for block cyclic and convolution codes.
Signal Processing, 86, .
Abstract
We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes.
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Published date: 2006
Keywords:
Viterbi decoding, BCH codes, Field Programmable Gate Array, parallel algorithms
Organisations:
EEE
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Local EPrints ID: 262273
URI: http://eprints.soton.ac.uk/id/eprint/262273
ISSN: 0165-1684
PURE UUID: 40977291-2a46-4e53-b9a5-dca94e56827e
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Date deposited: 05 Apr 2006
Last modified: 14 Mar 2024 07:08
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Contributors
Author:
Jeffrey Reeve
Author:
Kosala Amarasinghe
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