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Thermal-aware SoC test scheduling with test set partitioning and interleaving

Thermal-aware SoC test scheduling with test set partitioning and interleaving
Thermal-aware SoC test scheduling with test set partitioning and interleaving
SoC test, thermal-aware
Zhiyuan, He
4cb7660a-f1ce-459f-9679-1b6f3f14375e
Peng, Zebo
c0500005-3976-42df-974f-581eb1d39589
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhiyuan, He
4cb7660a-f1ce-459f-9679-1b6f3f14375e
Peng, Zebo
c0500005-3976-42df-974f-581eb1d39589
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Zhiyuan, He, Peng, Zebo, Eles, Petru, Rosinger, Paul and Al-Hashimi, Bashir M. (2006) Thermal-aware SoC test scheduling with test set partitioning and interleaving. ”, International Symposium on Defect and Fault Tolerance in VLSI System, Washington DC. 03 - 04 Oct 2006.

Record type: Conference or Workshop Item (Paper)
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More information

Published date: 2006
Additional Information: Event Dates: 3-4 October 2006
Venue - Dates: ”, International Symposium on Defect and Fault Tolerance in VLSI System, Washington DC, 2006-10-03 - 2006-10-04
Keywords: SoC test, thermal-aware
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 262882
URI: http://eprints.soton.ac.uk/id/eprint/262882
PURE UUID: 822a171b-88e3-4875-b223-ee1c0ed93599

Catalogue record

Date deposited: 04 Aug 2006
Last modified: 14 Mar 2024 07:19

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Contributors

Author: He Zhiyuan
Author: Zebo Peng
Author: Petru Eles
Author: Paul Rosinger
Author: Bashir M. Al-Hashimi

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