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A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls

A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls
A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls
This work addresses a fundamental problem of vertical MOSFETS, that is, inherently deep junctions that exacerbate short channel effects (SCE). A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and the shallow drain junction is then formed by out-diffusion from an overlying poly-crystalline drain contact region. The efficacy of the approach is demonstrated by simulation and the influence of the JS on SCE clearly shown. The process has been used to produce experimental devices that are characterized and discussed in the context of the modeling.
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Tan, L., Buiu, O., Hall, S., Gili, E. and Ashburn, P. (2006) A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls. 8th International Conference on Solid State Electronics & Integrated Technology, Shanghai, China. 22 - 25 Oct 2006.

Record type: Conference or Workshop Item (Poster)

Abstract

This work addresses a fundamental problem of vertical MOSFETS, that is, inherently deep junctions that exacerbate short channel effects (SCE). A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and the shallow drain junction is then formed by out-diffusion from an overlying poly-crystalline drain contact region. The efficacy of the approach is demonstrated by simulation and the influence of the JS on SCE clearly shown. The process has been used to produce experimental devices that are characterized and discussed in the context of the modeling.

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More information

Published date: 2006
Additional Information: Event Dates: October 23rd - 26th
Venue - Dates: 8th International Conference on Solid State Electronics & Integrated Technology, Shanghai, China, 2006-10-22 - 2006-10-25
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 263253
URI: http://eprints.soton.ac.uk/id/eprint/263253
PURE UUID: 8218bf36-f64d-41c0-aae8-07f1103e3d99

Catalogue record

Date deposited: 18 Dec 2006
Last modified: 10 Dec 2021 21:35

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Contributors

Author: L. Tan
Author: O. Buiu
Author: S. Hall
Author: E. Gili
Author: P. Ashburn

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