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An Integrated High-level On-line Test Synthesis Tool

Oikonomakos, Petros and Zwolinski, Mark, Jha, Niraj(ed.) (2006) An Integrated High-level On-line Test Synthesis Tool IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 25, (11), pp. 2479-2491.

Record type: Article


Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. We consider on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source behavioral HDL code. This is enabled by introducing a metric for on-line testability. A new variation of duplication (namely inversion testing) is also proposed and used, providing the system with an additional degree of freedom for minimizing hardware overheads associated with test resource insertion. Considering on-line testability within the synthesis process facilitates fast and painless design space exploration, resulting in a versatile high-level synthesis process, capable of producing alternative realizations according to the designer’s directions, for alternative target technologies. Finally, the fault escape probability of the overall scheme is discussed theoretically and evaluated experimentally.

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Published date: November 2006
Keywords: Test synthesis, High level synthesis, Design for testability, Dataflow synthesis
Organisations: EEE


Local EPrints ID: 263408
ISSN: 0278-0070
PURE UUID: 0f42856a-d128-40bf-913b-811ecc8d92e0
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 12 Feb 2007
Last modified: 18 Jul 2017 07:45

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Author: Petros Oikonomakos
Author: Mark Zwolinski ORCID iD
Editor: Niraj Jha

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