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On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder

On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the Add-Compare-Select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm2 and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW / Mbps
Viterbi decoder, low power, WLAN
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Kristic, Milos
5f7e7d30-61f4-43ce-805c-8c0e4f1d0f07
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Kristic, Milos
5f7e7d30-61f4-43ce-805c-8c0e4f1d0f07
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1

Maharatna, Koushik, Troya, Alfonso, Kristic, Milos and Grass, Eckhard (2006) On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder. 19th VLSI Design Conference 2006, India.

Record type: Conference or Workshop Item (Paper)

Abstract

This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the Add-Compare-Select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm2 and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW / Mbps

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More information

Published date: 2006
Venue - Dates: 19th VLSI Design Conference 2006, India, 2006-01-01
Keywords: Viterbi decoder, low power, WLAN
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263536
URI: https://eprints.soton.ac.uk/id/eprint/263536
PURE UUID: 86e6f86f-4c01-41db-ad1b-423a7008d1b9

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Date deposited: 19 Feb 2007
Last modified: 19 Jul 2019 22:28

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