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Dual Mode Synchronous/Asynchronous CORDIC Processor

Dual Mode Synchronous/Asynchronous CORDIC Processor
Dual Mode Synchronous/Asynchronous CORDIC Processor
For application in a software defined radio a CORDIC processor has been developed that can operate both in synchronous and in asynchronous mode. Each mode of operation has advantages and drawbacks. Depending on the actual application an optimal trade-off can be achieved for a complete system by choosing the appropriate mode of operation . We believe that this additional degree of freedom significantly increases the application space for potential users. The design has been implemented on a 0.25 µm SiGe BiCMOS process. Simulation results using post-layout extracted parameters indicate that the design is competitive both with purely synchronous and purely asynchronous implementations.
Asynchronous, CORDIC, sine/cosine genrator
76-83
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Sarker, Bodhisatwa
9ab92809-e93d-489a-ba2b-d6aa87de9640
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Sarker, Bodhisatwa
9ab92809-e93d-489a-ba2b-d6aa87de9640
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd

Grass, Eckhard, Sarker, Bodhisatwa and Maharatna, Koushik (2002) Dual Mode Synchronous/Asynchronous CORDIC Processor. 8th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2002, United Kingdom. pp. 76-83 .

Record type: Conference or Workshop Item (Paper)

Abstract

For application in a software defined radio a CORDIC processor has been developed that can operate both in synchronous and in asynchronous mode. Each mode of operation has advantages and drawbacks. Depending on the actual application an optimal trade-off can be achieved for a complete system by choosing the appropriate mode of operation . We believe that this additional degree of freedom significantly increases the application space for potential users. The design has been implemented on a 0.25 µm SiGe BiCMOS process. Simulation results using post-layout extracted parameters indicate that the design is competitive both with purely synchronous and purely asynchronous implementations.

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More information

Published date: 2002
Venue - Dates: 8th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2002, United Kingdom, 2002-01-01
Keywords: Asynchronous, CORDIC, sine/cosine genrator
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263556
URI: https://eprints.soton.ac.uk/id/eprint/263556
PURE UUID: 31ce56a2-0d31-44a2-a2a4-257b3f6e7873

Catalogue record

Date deposited: 19 Feb 2007
Last modified: 19 Jul 2019 22:28

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