Low Power CORDIC Processor Design Using Transmission Gate Logic on Sea of Gates


Maharatna, Koushik and Banerjee, Swapna (1999) Low Power CORDIC Processor Design Using Transmission Gate Logic on Sea of Gates At Int’l Conference on Modeling Simulation and Communication (CMSC) 1999, India.

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Item Type: Conference or Workshop Item (Paper)
Venue - Dates: Int’l Conference on Modeling Simulation and Communication (CMSC) 1999, India, 1999-01-01
Organisations: Electronic & Software Systems
ePrint ID: 263561
Date :
Date Event
1999Published
Date Deposited: 19 Feb 2007
Last Modified: 17 Apr 2017 19:50
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/263561

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