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Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Ahmadi, Arash and Zwolinski, Mark (2007) Multiple-Width Bus Partitioning Approach to Datapath Synthesis At IEEE International Symposium on Circuits and Systems (ISCAS), United States. 27 - 30 May 2007. , 2994 -2997.

Record type: Conference or Workshop Item (Paper)


A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the FUs as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a Multi-Objective Optimization Genetic Algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting an optimal grouping and word-length for each FU in a shared bus system. Results demonstrate that savings can be made in the overall system costs by applying this method.

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Published date: 2007
Additional Information: Event Dates: 27-30 May 2007
Venue - Dates: IEEE International Symposium on Circuits and Systems (ISCAS), United States, 2007-05-27 - 2007-05-30
Organisations: EEE


Local EPrints ID: 263741
ISBN: 978-1-4244-0920-4
PURE UUID: cdba9fd0-e5dd-4740-9861-738502855b1c
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 23 Mar 2007
Last modified: 18 Jul 2017 07:42

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Author: Arash Ahmadi
Author: Mark Zwolinski ORCID iD

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