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A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware

Ahmadi, Arash and Zwolinski, Mark (2007) A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware At International Symposium on Integrated Circuits (ISIC 2007), Singapore. 26 - 28 Sep 2007. , pp. 497-500.

Record type: Conference or Workshop Item (Paper)

Abstract

This paper addresses the problem of choosing different word-lengths for each functional unit in fixed-point implementations of DSP algorithms. A symbolic-noise analysis method is introduced for high-level synthesis of DSP algorithms in digital hardware, together with a vector evaluated genetic algorithm for multiple objective optimization. The ability of this method to combine word-length optimization with high-level synthesis parameters and costs to minimize the over all design cost is demonstrated by example designs.

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More information

Published date: 28 September 2007
Additional Information: Event Dates: 26-28 September 2007
Venue - Dates: International Symposium on Integrated Circuits (ISIC 2007), Singapore, 2007-09-26 - 2007-09-28
Organisations: EEE

Identifiers

Local EPrints ID: 264037
URI: http://eprints.soton.ac.uk/id/eprint/264037
ISBN: 978-1-4244-0796-5
PURE UUID: a32e6ea4-4cca-460a-893b-d56181dfd19a
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 22 May 2007
Last modified: 18 Jul 2017 07:40

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Contributors

Author: Arash Ahmadi
Author: Mark Zwolinski ORCID iD

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