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Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package
Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package
According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 µm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-µm-pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.
high speed electronic packaging, wafer level packaging.
413-425
Tay, Andrew
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Iyer, Mahadevan
c3d63173-2236-4774-89fb-a82594ddc6ed
Tummala, Rao
1341eb5d-c0fd-4ce7-bfd9-9cd714513028
Kripesh, V
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Wong, E.H.
2aced162-d424-41bd-b986-9b935d421af0
Swaminathan, Madhavan
0fb433b4-5d2b-4ef4-9b62-c99969d948d9
Wong, C.P.
a2f783e5-6a2e-4765-bd49-f3a694606a3a
Rotaru, Mihai D.
c53c5038-2fed-4ace-8fad-9f95d4c95b7e
Doraiswami, Ravi
b9e6042c-bc3c-46c8-8db5-c48bae66936e
Ang, Simon
78e2f99b-d9e5-45cf-9190-bbd7a15abaa1
Tay, Andrew
3f63c90c-9037-4ea7-af93-d03eec84c719
Iyer, Mahadevan
c3d63173-2236-4774-89fb-a82594ddc6ed
Tummala, Rao
1341eb5d-c0fd-4ce7-bfd9-9cd714513028
Kripesh, V
d2b9f61b-22f6-4800-8f7f-adb20ac9ef99
Wong, E.H.
2aced162-d424-41bd-b986-9b935d421af0
Swaminathan, Madhavan
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Wong, C.P.
a2f783e5-6a2e-4765-bd49-f3a694606a3a
Rotaru, Mihai D.
c53c5038-2fed-4ace-8fad-9f95d4c95b7e
Doraiswami, Ravi
b9e6042c-bc3c-46c8-8db5-c48bae66936e
Ang, Simon
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Tay, Andrew, Iyer, Mahadevan, Tummala, Rao, Kripesh, V, Wong, E.H., Swaminathan, Madhavan, Wong, C.P., Rotaru, Mihai D., Doraiswami, Ravi and Ang, Simon (2004) Next Generation of 100-μm-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package. IEEE Transactions on Advanced Packaging, Vol 27 (No 2), 413-425.

Record type: Article

Abstract

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 µm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-µm-pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.

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More information

Published date: May 2004
Keywords: high speed electronic packaging, wafer level packaging.
Organisations: EEE

Identifiers

Local EPrints ID: 264133
URI: http://eprints.soton.ac.uk/id/eprint/264133
PURE UUID: 544232e9-8584-4c94-8581-94c41b4c817e

Catalogue record

Date deposited: 08 Jun 2007
Last modified: 14 Mar 2024 07:42

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Contributors

Author: Andrew Tay
Author: Mahadevan Iyer
Author: Rao Tummala
Author: V Kripesh
Author: E.H. Wong
Author: Madhavan Swaminathan
Author: C.P. Wong
Author: Mihai D. Rotaru
Author: Ravi Doraiswami
Author: Simon Ang

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