Next Generation of 100-um-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package

Tay, Andrew, Iyer, Mahadevan, Tummala, Rao, Kripesh, V, Wong, E.H., Swaminathan, Madhavan, Wong, C.P., Rotaru, Mihai D., Doraiswami, Ravi and Ang, Simon (2004) Next Generation of 100-um-Pitch Wafer-Level Packaging and Assembly for Systems-on-Package IEEE Transactions on Advanced Packaging, Vol 27, (No 2), pp. 413-425.


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According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 um by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-um-pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final “optimum” design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with coefficient of thermal expansion of 10 ppm/K or lower.

Item Type: Article
Keywords: high speed electronic packaging, wafer level packaging.
Organisations: EEE
ePrint ID: 264133
Date :
Date Event
May 2004Published
Date Deposited: 08 Jun 2007
Last Modified: 17 Apr 2017 19:43
Further Information:Google Scholar

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