Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

Kripesh, Vaidyanathan, Yoon, Seung Wook, Ganesh, V. P., Khan, Navas, Rotaru, Mihai D, Fang, Wang and Iyer, Mahadevan (2005) Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28, (3), pp. 377-386.


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In this paper, a novel method of fabricating three– dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP

Item Type: Article
ISSNs: 1521-3323 (print)
Keywords: Three-dimensional system-in-package (3-D SiP), stacked modules, through wafer interconnection, wafer thinning, integrated cooling solution.
Organisations: EEE
ePrint ID: 264157
Date :
Date Event
August 2005Published
Date Deposited: 11 Jun 2007
Last Modified: 17 Apr 2017 19:42
Further Information:Google Scholar

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