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Efficient inner-receiver design for OFDM-based WLAN systems: Algorithm and architecture

Efficient inner-receiver design for OFDM-based WLAN systems: Algorithm and architecture
Efficient inner-receiver design for OFDM-based WLAN systems: Algorithm and architecture
In this article we propose a complete solution for the so-called Inner Receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. Our work has been divided into two parts. In this Part – I we concentrate our investigations on three key components forming the Inner Receiver namely, the Synchronizer, the Channel Estimator and the Digital Timing Loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our proposals.
Channel Estimation, OFDM, Synchronization, Wireless LAN
1374-1385
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Krstic, Milos
bd460841-d42a-4a4b-b440-096f2a09f236
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Jagdhold, Ulrich
f6a767c0-c566-487b-9088-beb92b7df066
Kraemer, Rolf
b8e92586-086e-49a2-9df7-483820736f89
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Krstic, Milos
bd460841-d42a-4a4b-b440-096f2a09f236
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Jagdhold, Ulrich
f6a767c0-c566-487b-9088-beb92b7df066
Kraemer, Rolf
b8e92586-086e-49a2-9df7-483820736f89

Troya, Alfonso, Maharatna, Koushik, Krstic, Milos, Grass, Eckhard, Jagdhold, Ulrich and Kraemer, Rolf (2007) Efficient inner-receiver design for OFDM-based WLAN systems: Algorithm and architecture. IEEE Transactions on Wireless Communications, 6 (4), 1374-1385.

Record type: Article

Abstract

In this article we propose a complete solution for the so-called Inner Receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. Our work has been divided into two parts. In this Part – I we concentrate our investigations on three key components forming the Inner Receiver namely, the Synchronizer, the Channel Estimator and the Digital Timing Loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our proposals.

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More information

Published date: April 2007
Keywords: Channel Estimation, OFDM, Synchronization, Wireless LAN
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 264325
URI: https://eprints.soton.ac.uk/id/eprint/264325
PURE UUID: c475cf9a-67d7-4d88-93d8-9b6011f3d4a3

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Date deposited: 14 Aug 2007
Last modified: 19 Jul 2019 22:26

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Contributors

Author: Alfonso Troya
Author: Milos Krstic
Author: Eckhard Grass
Author: Ulrich Jagdhold
Author: Rolf Kraemer

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