The role of tunnel barriers in Phase-State Low Electron-Number Drive Transistors (PLEDTRs)
The role of tunnel barriers in Phase-State Low Electron-Number Drive Transistors (PLEDTRs)
This paper presents a numerical analysis of the role of tunnel barriers in explaining the experimental I-V characteristics of a new vertical tunnel transistor called Phase-state Low Electron-number Drive Transistor (PLEDTR), used for constructing a high-speed and high-capacity gain cell. Introducing the characteristic features of tunneling current through ultrathin barriers into a standard two-dimensional (2-D) drift-diffusion (DD) device simulator by way of calibrating it with a self-consistent one-dimensional (1-D) Poisson/Shrodinger equation solver, it is shown that the transistor characteristics on the ON-state are substantially affected by the thickness of the source barrier. Asymmetric source and drain barrier (SDBs)structures are found to be responsible for the large asymmetry of the I-V characteristics at large source-drain voltages found experimentally. It is also shown that the central shutter barriers (CSBs) reduce the overall drain current in the sub-threshold regime, leading to superior OFF current characteristics.
Semiconductor device modelling, semiconductor memories, tunnel transistors, tunneling
1103-1108
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Wagner, Mathias
3e68f3fa-d1e0-4671-9586-dcd6531a0efc
Nakazato, Kazuo
6aa559c1-c8c0-4ca3-880e-bca6f0c70642
June 2001
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Wagner, Mathias
3e68f3fa-d1e0-4671-9586-dcd6531a0efc
Nakazato, Kazuo
6aa559c1-c8c0-4ca3-880e-bca6f0c70642
Mizuta, Hiroshi, Wagner, Mathias and Nakazato, Kazuo
(2001)
The role of tunnel barriers in Phase-State Low Electron-Number Drive Transistors (PLEDTRs).
IEE Trans Electron Devices, 48 (6), .
Abstract
This paper presents a numerical analysis of the role of tunnel barriers in explaining the experimental I-V characteristics of a new vertical tunnel transistor called Phase-state Low Electron-number Drive Transistor (PLEDTR), used for constructing a high-speed and high-capacity gain cell. Introducing the characteristic features of tunneling current through ultrathin barriers into a standard two-dimensional (2-D) drift-diffusion (DD) device simulator by way of calibrating it with a self-consistent one-dimensional (1-D) Poisson/Shrodinger equation solver, it is shown that the transistor characteristics on the ON-state are substantially affected by the thickness of the source barrier. Asymmetric source and drain barrier (SDBs)structures are found to be responsible for the large asymmetry of the I-V characteristics at large source-drain voltages found experimentally. It is also shown that the central shutter barriers (CSBs) reduce the overall drain current in the sub-threshold regime, leading to superior OFF current characteristics.
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Published date: June 2001
Keywords:
Semiconductor device modelling, semiconductor memories, tunnel transistors, tunneling
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 264336
URI: http://eprints.soton.ac.uk/id/eprint/264336
PURE UUID: e2831443-793e-4572-8fca-7789951bb714
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Date deposited: 24 Jul 2007
Last modified: 14 Mar 2024 07:47
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Contributors
Author:
Hiroshi Mizuta
Author:
Mathias Wagner
Author:
Kazuo Nakazato
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