Serialized Asynchronous Links for NoC
Serialized Asynchronous Links for NoC
This paper proposes an asynchronous serialized link for NoC that can achieve the same levels of performance in terms of flits per second as a synchronous link but with a reduced number of wires in the point to point switch links and reduced power consumption. This is achieved by employing serialization in the asynchronous domain as opposed to synchronous to facilitate the removal of global clocking on the serial links. Based on transistor level simulations using 0.12 ?m foundry models it has been shown that it is possible to achieve the same level of performance as synchronous but with 75% reduction in wires and 65% reduction in power for a 300 MFlit/s link with 8 buffers with a switch clock speed of 300 MHz. Furthermore the paper presents the design requirements arising from interfacing switches of synchronous NoC and asynchronous serial links.
Ogg, Simon
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Valli, Enrico
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Al-Hashimi, Bashir
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Yakovlev, Alex
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D'Alessandro, Crescenzo
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Benini, Luca
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March 2008
Ogg, Simon
a3638098-5456-4ac5-95fe-7425f0264401
Valli, Enrico
923fcf3a-ba64-4036-b04c-ea13a26f1b5b
Al-Hashimi, Bashir
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Yakovlev, Alex
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D'Alessandro, Crescenzo
abbc0fa9-88d4-4087-9494-7e26c29638c2
Benini, Luca
158d569b-b7d4-4d91-9935-4267ea8fd494
Ogg, Simon, Valli, Enrico, Al-Hashimi, Bashir, Yakovlev, Alex, D'Alessandro, Crescenzo and Benini, Luca
(2008)
Serialized Asynchronous Links for NoC.
DATE, Munich.
Record type:
Conference or Workshop Item
(Paper)
Abstract
This paper proposes an asynchronous serialized link for NoC that can achieve the same levels of performance in terms of flits per second as a synchronous link but with a reduced number of wires in the point to point switch links and reduced power consumption. This is achieved by employing serialization in the asynchronous domain as opposed to synchronous to facilitate the removal of global clocking on the serial links. Based on transistor level simulations using 0.12 ?m foundry models it has been shown that it is possible to achieve the same level of performance as synchronous but with 75% reduction in wires and 65% reduction in power for a 300 MFlit/s link with 8 buffers with a switch clock speed of 300 MHz. Furthermore the paper presents the design requirements arising from interfacing switches of synchronous NoC and asynchronous serial links.
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08.4_3_0493.pdf
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Published date: March 2008
Additional Information:
Event Dates: 2008
Venue - Dates:
DATE, Munich, 2008-01-01
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 265014
URI: http://eprints.soton.ac.uk/id/eprint/265014
PURE UUID: 6f4d1ad4-0da9-472d-9db7-51e932776aca
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Date deposited: 07 Jan 2008 16:31
Last modified: 14 Mar 2024 08:00
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Contributors
Author:
Simon Ogg
Author:
Enrico Valli
Author:
Bashir Al-Hashimi
Author:
Alex Yakovlev
Author:
Crescenzo D'Alessandro
Author:
Luca Benini
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